Understanding Cryptography by Christof Paar and Jan Pelzl - Chapter 3 Solutions - Ex3.10- 2 mins
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- Exercise 3.1
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- Exercise 3.10
- Exercise 3.11
- Exercise 3.12
- Exercise 3.13
In this problem we want to study the clock frequency requirements for a hardware implementation of DES in real-world applications. The speed of a DES implementation is mainly determined by the time required to do one core iteration. This hardware kernel is then used 16 consecutive times in order to generate the encrypted output. (An alternative approach would be to build a hardware pipeline with 16 stages, resulting in 16-fold increased hardware costs.)
- Let’s assume that one core iteration can be performed in one clock cycle. Develop an expression for the required clock frequency for encrypting a stream of data with a data rate r [bit/sec]. Ignore the time needed for the initial and final permutation.
- What clock frequency is required for encrypting a fast network link running at a speed of 1 Gb/sec? What is the clock frequency if we want to support a speed of 8 Gb/sec?
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1. If one round of encryption is performed each clock cycle, then we can say that 64 bits of data are encrypted in 16 clock cycles. As such, we can calculate the number of bits encrypted per clock cycle:
As such, the throughput in bits for a given clock speed can be calculated as follows:
2. In order to calculate the clock speed required for a given bitrate, we need to rearrange the above equation:
For 1 Gb of throughput per second, we need a clock speed of:
For 8 Gb of throughput per second, we need a clock speed of: